The present invention relates to a method and/or architecture for watchdog timers generally and, more particularly, to a method and/or architecture for implementing a Phase Locked Loop (PLL) lockout watchdog timer.
A lockout (or runaway) condition occurs in a PLL following fault clearing when a circuit will not attempt to reclose (i.e., recover or re-acquire) the loop. Transformers, generators, and buses typically trip once and lockout immediately. Transmission lines and distribution lines will generally attempt one or more recloses (recoveries), and will then lockout if the fault remains following the last unsuccessful recovery attempt in the sequence. Conventional correction methods for lookout conditions typically require a reset of the device.
Referring to FIG. 1, a conventional PLL lock detector circuit 10 is shown. The circuit 10 has the disadvantages of not distinguishing between lockout, powerup, and frequency acquisition. The circuit 10 cannot detect when a PLL is locked on a harmonic. Furthermore, the circuit 10 requires additional circuitry to recover from a lockout.
The present invention concerns a circuit that may be configured to detect a lockout condition of a phase lock loop (PLL) circuit. The circuit may be configured to forcibly correct an operating frequency of the PLL circuit.
The objects, features and advantages of the present invention include providing a PLL lockout watchdog that may (i) detect a lockout (e.g., a runaway) condition; (ii) detect and correct a lockout (runaway) condition; and (iii) switch to a recovery feedback path during a first mode (e.g., a lockout).